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1 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 advanced information highly intergated 10/100m dual speed hub with extra 4 port switch built-in 1. features ? integrate a 4-port switch core and a 12-port dual-speed repeater core. ? support 0 to 4 mii switch ports and 6 to 8 mii/rmii repeater ports and 10/100m expansion ports. configure by mode select. ? each switch port can operate in 10/100, half/full duplex mode, auto-configured by a n-way phyceiver. ? each repeater port auto-sense line speed (10/100m), and operate in half-duplex mode. ? provide 10m and 100m expansion buses for stacking up to 9 hubs. ? provide link/activity, partition, utilization led display function for diagnostic purpose. 2. general description the MX98748 is a fast ethernet product with 4 port switch and 8 port repeater hub controller. by mode select, it can offer different type of switch and hub port configura- tion such as 2sw/8hubport, 3sw/7hub port, 4sw/ 6hub port seperately. combine with mx98747 - 8 ports dual speed repeater controller, customer can design di- ? the embedded switch operates in store-and-forward mode ? support up to 2k address entries without external address look-up ic ? single 64kx32 ssram part used as data buffering and filtering database for the embedded switch. ? ieee802.3x flow control for full-duplex switch port. ? backpressure flow control for half-duplex switch port. ? provide rx-buffer-threshold control and tx-buffer- threshold control to avoid any port occupying all buffer resource. ? support serial eeprom interface for power on configu- ration verse hibrid hub ( hub with switch function) products such as 16rpt port + 2 switch ports, 24rpt port + 2 switch ports,and etc.(more information on application configu- ration can be found in application note and MX98748 presentation material.)
2 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 3.0 block diagram sram control & arbiter ma md control mode(3:0) clk50m, reset# led & control mdc,mio 100m expansion 10m expansion broadcast descriptior control ecs. esk(clk),edi/o mii s/w port0 mii s/w porti serial eeprom interface mii/rmii port7(sw-port3) mii/rmii port6(sw-port2) mii/rmii port5 mii/rmii port4 mii/rmii port3 mii/rmii port2 mii/rmii port1 mii/rmii port0 empty list(qm) arl control mac-0 mac-3 mode select sys clk & rst 10m port 10m repeater core sw port3 sw port2 mux for port switch 10m exp. sw/rpt port mux mac-2 mac-1 100m port 100m repeater core mii management & control 100m exp. led control
3 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 3.1 typical application mii interface: 50 mhz osc. buffer 50mhz mii mii mii mii MX98748 phy quad phy rj-45 txformer x10 1/2 phy quad phy 64k x 32 ssram rmii interface: 50 mhz osc. buffer 50mhz mii rmii rmii mii MX98748 phy quad phy rj-45 txformer x10 1/2 phy quad phy 64k x 32 ssram
4 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 4.0 system implementation block diagram 10m exp q-phy 01 2 3 q-phy 45 67* 100m exp expansion bus for stackable solution phy port sw3 sw2 sw1 mux phy phy ssram MX98748 sw0
5 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 5.0 pin configuration 14 18 6 10 2 4 22 26 30 34 38 42 46 50 54 58 61 63 64 65 e f c d a b g h j k l m n p r t u v w y 13 17 5 9 256 1 21 25 29 33 37 41 45 49 53 57 60 62 66 67 12 16 3 8 255 254 20 24 28 32 36 40 44 48 52 56 59 68 69 70 11 15 251 7 253 252 19 23 27 31 35 39 43 47 51 55 71 72 73 74 248 247 250 249 75 76 77 78 244 243 246 245 79 80 81 82 240 239 242 241 83 84 85 86 236 235 238 237 v3 v1 v1 v1 v1 g 87 88 89 90 232 231 234 233 v3 v1 v1 v1 v1 g 91 92 93 94 228 227 230 229 v3 g g g g g 95 96 97 98 224 223 226 225 v3 g g g g g 99 100 101 102 220 219 222 221 v3 v2 v2 v2 v2 g 103 104 105 106 216 215 218 217 v3 v2 v2 v2 v2 g 107 108 109 110 212 211 214 213 111 112 113 114 208 207 210 209 115 116 117 118 204 203 206 205 119 120 121 122 183 179 200 199 202 201 175 171 167 163 159 155 151 147 143 139 135 123 124 125 184 180 196 187 198 197 176 172 168 164 160 156 152 148 144 140 136 132 126 127 185 181 190 188 195 194 177 173 169 165 161 157 153 149 145 141 137 133 130 128 186 182 191 189 193 1 2 3 4 5 6 7 8 9 1011121314151617181920 192 178 174 170 166 162 158 154 150 146 142 138 134 131 129
6 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 6.0 pin description a.switch mii port, 35 pins pin name pin type bga # description s1txd[3:0] o, 4ma 159-162 switch mii transmit data. s2txd[3:0] 95-98 s1txen o, 4ma 171 switch mii transmit enable. s2txen 106 s1txclk i, ttl, dn 172 switch mii transmit clock. s2txclk 107 s1crs i, ttl, dn 157 switch mii carrier sense. s2crs 93 s1rxdv i, ttl, dn 175 switch mii receive data valid. s2rxdv 110 s1col i, ttl, dn 158 switch mii collision input. high if network has collision. s3col s2col 94 input from link[6] in mode (1100,1101) s4col 138 s1rxclk i, ttl, dn 174 switch mii receive clock. s2rxclk 109 s1rxd[3:0] i, ttl, dn 179-176 switch mii 4b receive data. s2rxd[3:0] 114-111 s1rxer i, ttl, dn 173 switch mii receive error. s2rxer 108 duplex1 i, ttl, dn 140 switch mii duplex input. high for half duplex, low for full duplex. duplex2 141 and this polarity can be change by register 0.8. duplex3 input duplex4 139 from link[7] in mode(1100,1101) lswbuff o, 16ma 126 switch ssram buffer full led output. low active. active when the buffer is full. b. switch ssram interface, 50 pins pin name pin type bga # description ma[15:0] o, 4ma 210-217 switch ssram address outputs. 225-232 md[31:0] i/o,ttl,4ma 38-31 switch ssram data i/o. 26-19 7-256 246-240 gwx o, 8ma 202 switch ssram write enable. (low active) cex o, 8ma 204 switch ssram chip enable. (low active)
7 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 c. eeprom interface, 6 pins pin name pin type bga # description ecs/test0 i/o,ttl,4ma 122 eeprom chip select. input for test mode selection when resetl active. esk/test1 i/o,ttl,4ma 123 eeprom clock. input for test mode selection when resetl active. edi/test2 i/o,ttl,4ma 124 eeprom data in. input for test mode selection when resetl active. edo i/o,ttl,4ma 125 eeprom data output. eeprom i,ttl 203 high for eeprom present. eemaster i,ttl 163 eeprom master. if high, MX98748 will work as the master of eeprom interface; if low, it will work in slave mode of eeprom interface. note: (test0, test1, test2)=(0,0,0) in normal operation.
8 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 d. repeater hub mii/rmii port, 120 pins pin name pin type bga # description txd0[3:0] o,4ma 253-255,8 repeater transmit data. port7 ~ port0 txd1[3:0] 28-30,39 txd2[3:0] 50-53 txd3[3:0] 65-68 txd4[3:0] 80-83 txd5[3:0] 100-103 txd6[3:0] 165-168 txd7[3:0] 189-192 txen[7:0] o ,4ma 193,169,104, repeater transmit enable. 84, 69, 54, 40, 9 txclk[7:0] i,ttl 194,170,105, repeater transmit clock. 85, 70, 55, 41, 10 link[7:0] i,ttl 137, 136, 133, repeater link good. low for link good. if high over 192ms, 128,78, 56, a link fail will detect. 127, 18 crs[7:0] i,ttl 188, 164, 99, 79, repeater carrier sense. 64, 49, 27, 252 rxdv[7:0] i,ttl 197, 183, 117, repeater receive data valid. also speed input in rmii mode, 88,73, 59, 44, low for speed 100m. 13 rxclk[7:0] i,ttl 196, 182, 116, 87, repeater receive clock. 72, 58, 43, 12 rxer[7:0] i,ttl 195, 181, 115, 86, repeater receive error. if true, a jam pattern will send out 71, 57, 42, 11 through that packet. rxd0[3:0] i,ttl 17-14 repeater receive data. port7 ~ port0 rxd1[3:0] 48-45 rxd2[3:0] 63-60 rxd3[3:0] 77-74 rxd4[3:0] 92-89 rxd5[3:0] 121-118 rxd6[3:0] 150-147 rxd7[3:0] 165-162
9 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 e. repeater hub led & control, 14 pins pin name pin type bga # description ledinf[7:0] i/o,ttl,16ma 142-150 repeater led information output (normal mode).in scan mode, ledinf output 10/100m core state information. in power on jumper mode, set each port control register. lnkactsel parsel 0 0 ----normal 0 1 ----partition disable 1 0 ----jabber disable 1 1 ----speed set led10col o ,16ma 135 repeater 10m collision led output. low active also it is 10m core state jam or quiet indicator in scan mode. led100col o ,16ma 134 repeater 100m collision led output. low active.also it is 100m core state jam or quiet indicator in scan mode. lnkactsel i/o,ttl,4ma 132 repeater ledinf link/act rising latch clock (normal mode) also power on jumper mode setting, see ledinf. parsel i/o,ttl,4ma 131 repeater ledinf partition rising latch clock (normal mode). also power on jumper mode setting, see ledinf. utl10sel i/o ,ttl,4ma 130 repeater ledinf 10m utilization rising latch clock (normal mode). in scan mode, 10m state output error/idle indicator. power on jam extension jumper mode setting. utl100sel i/o, ttl, 4ma 129 repeater ledinf 100m utilization rising latch clock (normal mode). in scan mode, 100m state output error/idle indicator. power on jam extension jumper mode setting.
10 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 f. 10/100m expansion port, 22 pins pin name pin type bga # description jamo10 o, 8ma 235 forced jam out. active high. the pin is asserted upon collision jamo100 207 detected or receive error. jami10 i,ttl,schm 236 forced jam input. active high. assert when other stacked jami100 208 hub detected a collision. epclk10 i/o,ttl,dn,8ma 238 expansion port data clock. use as receive or transmit expan- epclk100 219 sion port clock. erxdv10 i/o ,ttl,dn,8ma 239 expansion port data valid. erxdv100 220 e10dat[3:0] i/o,ttl,dn,8ma 224-221 expansion port 4b data. e100dat[3:0] 251-248 anyact10 o,8ma 234 any activity. active high. a or function result of crs[7:0]. to anyact100 206 tell other stacked hubs there are activities. to other stacked hub's edcrs. edcrs10 i,ttl,schm 237 expansion data carrier sense. active high, other stacked hubs' edcrs100 218 activities will pass on this pin. edact10 o,8ma 233 expansion data activity. system application use this pin to edact100 205 control data flow of edat, erxdv, epclk.
11 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 g. management interface & miscellaneous, 9 pins pin name pin type bga # desvription mdc i/o,ttl,dn,4ma 151 management data clock. mdio i/o,t tl,up,4ma 150 management data input/output. mode[3:0] i,ttl,dn 155-152 mode select. define MX98748 function 0000 normal - 2sw + 8mii hub ports 0001 scan - hub scan for debug use 0010 sw2rmii - 2sw + 8rmii hub ports 0011 fmode - hub high speed test mode 0110 sw4d10r- 3sw + 7rmii hub ports, internal 10m link dis- able 0111 sw4d10- 3sw + 7mii hub ports, internal 10m link disable 1010 sw3d100r - 3sw + 7rmii hub ports, internal 100m link disable 1011 sw3d100 - 3sw + 7rmii hub ports, internal 100m link disable 1100 sw4 - 4sw | 6mii hub ports with no internal link 1101 sw4r - 4sw | 6rmii hub ports with no internal link 1110 - test only 1111 - test only resetl i,ttl,schm 156 reset bar input. low active. must last more than 160ns. clk50m i,ttl,schm 180 chip 50mhz clock input. all100 tr i-state 209 if any repeater port in the hub is connected to 10 base, the pin will assert low, otherwise it will keep in high-z state. h. power & ground, 34 pins pin name pin type bga # desvription vdd = 3.3v i in center power. v1 ball gnd i in center ground. g ball
12 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 7.0 functional description the MX98748 is operating by a single 50mhz clock frequency. the MX98748 is a chip integrated with the 4-port switch and the 12-port repeater. mode[3:0] determines the major chip function whether it is a 2sw/8hub, 3sw/7hub, 4sw/6 hub ports. mode[3:0] also determines mii or rmii interface functions. each switch port can operate in 10/100m, half/full duplex mode. auto-configured by n-way phyceiver. each repeater port auto-detect line speed (10/100m), operate in half-duplex mode. the repeater also equiped with 10/100m expansion port for stackable solution. 9 hubs can be stacked through the expansion bus architecture. the mii management interface can program seeq 84225 quad phy into half duplex repeater mode after power on for hub application. one can also force the MX98748 internal register for each repeater port to control port behavior. the led interface provide link/activity, partition, utilization function diaplay of repeater hub. 7.1 mode seting the MX98748 function is determined by mode[3:0] as shown table below: mode name mode[3:0] function description normal 0000 nor mal mode, 2 sw + 8 mii hub ports scan 0001 t est only sw2rmii 0010 2 sw + 8 rmii hub ports fmode 0011 t est only - 0100 r eserve - 0101 r eserve sw4d10r 0110 3 sw + 7 rmii hub port, hub port 7 = sw4,internal 10m link disable sw4d10 0111 3 sw + 7 mii hub port, hub port 7 = sw4,internal 10m link disable - 1000 r eserve - 1001 r eserve sw3d100r 1010 3 sw + 7 rmii hub port, hub port 6 = sw3,internal 100m link disable sw3d100 1011 3 sw + 7 mii hub port, hub port 6 = sw3,internal 100m link disable seperate 1100 seperate 4 sw and 6 mii hub ports sep_rmii 1101 seperate 4 sw and 6 rmii hub ports test 1110 t est only test 1111 t est only when chip is under normal mode operation, there are extra 2 sw ports and 8 mii repeater ports from the application view point. under sw2rmii, same as normal except hub port is rmii interface. sw4d10r: disable10m phy mode link between switch and hub core internally. hub port 7 becomes swtich port 4. hub port 0-6 are rmii interface. sw4d10: the same as sw4d10r except hub port 0-6 are mii interface.
13 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 sw3d100r: disable100m phy mode link between switch and hub core internally. hub port 6 becomes swtich port 3. hub port 0-5, 7 are rmii interface. sw3d100: the same as sw3d100r except hub port 0-5, 7 are mii interface. seperate mode, there is no data link between switch and hub core. hub port 6, 7 become sw3 & sw4. the chip functions 4 switch ports and 6 hub ports. link[6] is s3col, link[7] is duplex3. sep_rmii: the same as seperate, except 6 hub ports are rmii interface. 7.2 eeprom pin function description eeprom = true means eeprom device present. 7.3 port function jumper mode description each port will set its port behavior depends on two control pin by power on latch. lnkactsel parsel function description 0 0 normal 0 1 partition disable 1 0 jabber disable 1 1 speed set. true=100m 7.4 end of jam extension jumper mode description end of jam extension can be alter by power on jumper setting. utl10sel utl100sel function description 0 0 extend 15 nibbles 0 1 extend 0 nibbles 1 0 extend 10 nibbles 1 1 extend 20 nibbles 7.5 switch function description
14 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 four ports switch are built-in on the MX98748. the unique features make the MX98748 can be easily used in dual speed hub application. two of the 4-ports switch are used internally to connect 10m segment and 100m segment. another extra two switch ports make the application of the chip diversely. four ported fast ethernet switch controller is embedded. the switchcore includes mac protocal, address resolution logic, buffer management and ssram controller. the mac block supports store-and-forward mode. both full duples flow control 802.3x and jam based flow control are supported. the transmit and receive beffer's threshold is programmable to avid only port occupying all buffer resource. the address resolution logic functions for address look up, learning, and aging. the address table is in external ssram and contains four layer of hash table. the buffer management includes broadcast descriptor and empty list(qm). each has several discriptors for man- agement. the ssram controller functions as follows. buffer memory is a 64k*32 ssram. the higher memory is used for address resolution table. the others are partitioned into 256 bytes/page for data and descriptor. each packet may use 1~6 page depends on packet size. each descriptor page includes 16 descriptors. memory size page size arl no. of page 64k*32 256byte 2k entries 960
15 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 7.5 internal register function description the internal register are addressed by the following address: 0x10 * (~eemaster) + offset offset is between 0x0 and oxf. 7.5.1 internal register format offset description default 0000(0x0) configuration register 0x1c00 0001(0x1) aging time. 10sec/per count 0x001e 0010(0x2) flow control pause counter 0x01ff 0011(0x3) mac id [15:0] for flow control 0x0000 0100(0x4) mac id [31:16] for flow control 0x0000 0101(0x5) mac id [47:32] for flow control 0x0000 0110(0x6) port 0 receive buffer threshold 0x0200 0111(0x7) port 1 receive buffer threshold 0x0200 1000(0x8) port 2 receive buffer threshold 0x0200 1001(0x9) port 3 receive buffer threshold 0x0200 1010(0xa) txthresh enable / port 0 transmit buffer threshold 0x2300 1011(0xb) txthresh enable / port 1 transmit buffer threshold 0x2300 1100(0xc) txthresh enable / port 2 transmit buffer threshold 0x2300 1101(0xd) txthresh enable / port 3 transmit buffer threshold0 0x2300 1110(0xe) multicast buffer threshold 0x2300 7.5.2 internal register description 7.5.2.1 configuration register default: 0x1c00 bit 3:0 : mbz : must be zero "0000 bit 5:4 : abortcnt : define the packets may be received after recive threshold is over. 00 : can receive 8 good packets after receive threshold over 01 : can receive 16 good packets after receive threshold over 10 : can receive 32 good packets after receive threshold over 11 : all good packets will be received after receive threshold over bit 7:6 : bpn : define the back-pressure-number of jamming the coming packets. 00 : back pressure count = 8 01 : back pressure count = 16 10 : back pressure count = 32 11 : back pressure count = infinite r mim c16d fce hash r dp bpn abortcnt mbz 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14
16 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 bit 8 : duplex polarity : 1 : input pin duplex high -> full, low -> half 0 : input pin duplex low -> full, high -> half bit 9 : reserved bit 11:10 : hash bits select. 0 : hash bits = crc bit 12:4 1 : hash bits = crc bit 18:10 2 : hash bits = crc bit 25:17 3 : hash bits = crc bit 31:23 bit 12 : full duplex flow control enable, high active. bit 13 : collision-16 disable, high active. bit 14 : management interface master enable, high active. bit 15 : reserved 7.5.2.2 ageing timer age timer 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 default : 0x001e bit 0:15 : agetimer : ageing timer 10 sec/per count 7.5.2.3 flow control pause time txfccnt 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 default: 0x01ff bit 0:15: txfccnt : flow control pause time 7.5.2.4 mac id [15:0] for flow control macid[15:0] 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 default: 0x0000 bit 0:15: macid[15:0] : mac id for flow control
17 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 7.5.2.5 mac id [31:16] for flow control macid[31:16] 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 7.5.2.6 mac id [47:32] for flow control macid[47:32] 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 default: 0x0000 bit 0:15: macid[31:16] : mac id for flow control default: 0x0000 bit 0:15: macid[47:32] : mac id for flow control 7.5.2.7 port 0 receive buffer threshold rx0 t hresh 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 rx1 t hresh 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 7.5.2.8 port 1 receive buffer threshold 7.5.2.9 port 2 receive buffer threshold rx2 t hresh 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 default: 0x0200 bit 0:12 : rx2thresh : port 2 receive buffer threshold. default: 0x0200 bit 0:12 : rx0thresh : port 0 receive buffer threshold. default: 0x0200 bit 0:12 : rx1thresh : port 1 receive buffer threshold.
18 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 7.5.2.10 port 3 receive buffer threshold rx3 t hresh 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 7.5.2.11 port 0 transmit buffer threshold and transmit threshold enable p0txthresh tte0 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 7.5.2.12 port 1 transmit buffer threshold and transmit threshold enable default: 0x2300 bit 0:12 : p2txthresh : port 2 transmit buffer thresh. bit 13 : tte2 : port 2 transmit threshold enable default: 0x0200 bit 0:12 : rx3thresh : port 3 receive buffer threshold. default: 0x2300 bit 0:12 : p0txthresh : port 0 transmit buffer thresh. bit 13 : tte0 : port 0 transmit threshold enable default: 0x2300 bit 0:12 : p1txthresh : port 1 transmit buffer thresh. bit 13 : tte1 : port 1 transmit threshold enable p1txthresh tte1 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 p2txthresh tte2 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 7.5.2.13 port 2transmit buffer threshold and transmit threshold enable
19 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 7.5.2.14 port 3 transmit buffer threshold and transmit threshold enable p3txthresh tte3 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 7.5.2.15 port 4 transmit buffer threshold and transmit threshold enable p5txthresh tte5 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 bit 0:12 : mtxthresh : multicast transmit buffer thresh. bit 13 : tte5 : multicast transmit threshold enable bit 0:12 : p3txthresh : port 3 transmit buffer thresh. bit 13 : tte3 : port 3 transmit threshold enable
20 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 8.0 absolute maximum operation rating rating v alue supply volatge(vcc) 3.0v to 4.0v dc input voltage(vin) -0.3v to vcc+0.3v dc output voltage (vout) -0.3v to vcc+0.3v storage temperature range(tstg) -55 c to 150 c power dissipation(pd) 800mw esd rating(rzap=1.5k, czap=100pf) 2000v absolute maximum rating for MX98748 notice: stresses greater than those listed under absolute maximum ratings may cauase permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. 9.0 ac/dc characteristic a.supply current symbol parameter conditions min. max. unit icc average active(txing/rxing) supply current x1=50mhz - - ma vin=switching iccidle average idle supply current x1=50mhz - - ma vin=vcc/gnd idd static idd current x1=undriven - - ma 9.1 dc characteristic b.ttl inputs, outputs tri-states symbol parameter conditions min. max. unit vil input low voltage - - 0.8 v vih input high voltage 2.0 vcc+0.3 v iin input current vi=vcc/gnd -1.0 1.0 v voh minimum high level ioh=-2ma/ output voltage -4ma/ 2.4 - v (others/mii/expansion) -8ma vol maximum low level iol=2ma/ output voltage 4ma/ - 0.4 v (others/mii/expansion) 8ma ioz maximum tri-state v out=vcc/ -10.0 10.0 ua output leakage current gnd
21 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 9.2 ac characterisitics a.mii management interface symbol description min. max. unit t01 period mdc 400 - ns t02 high time for mdc 160 - ns t03 low time for mdc 160 - ns t04 mdio setup to mdc rising edge(sourced by sta) 10 - ns t05 mdio hold to mdc rising edge(sourced by sta) 10 - ns t05 mdio to mdc rising edge (source by MX98748) 200 - ns figure 6-1 mdio timing relationship to mdc mdc mdio t04 t05 t02 t03 t01
22 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 symbol description(include switch & repeater port) min. typ. max. unit t11 receive clock period in 100m(note1) 39.998 40 40.002 ns t11 receive clock period in 10m(note1) 399.98 40 400.02 ns t11 clk50m period(note1) 19.999 20 20.001 ns t12 receive clock high time 0.35*t11 - - ns t13 receive clock low time 0.35*t11 - - ns t14 rxd[3:0]/rxdv/rxer setup time (mii interface) 5 - - ns t14 rxd[3:0]/rxdv/rxer setup time 2 - - ns (rmii interface repeater only) t15 rxd[3:0]/rxdv/rxer hold time(mii interface) 5 - - ns t15 rxd[3:0]/rxdv/rxer hold time 4 - - ns (rmii interface repeater only) figure 6-2 receive signal timing relationships at the mii/rmii note 1: the accurate receive clock frequency shall be 25mhz+/- 50ppm. clk50m should be 50mhz+/-50ppm. b.mii/rmii interface rxclk(mii) clk50m(rmii) rxd[3:0] rxdv rxer switch port or repeater port t13 t14 t15 t12 t11
23 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 symbol description(include switch & repeater port) min. typ. max. unit t21 transmit clock period in 100m(note1) 39.998 40 40.002 ns t21 transmit clock period in 10m(note1) 39.998 40 40.002 ns t21 clk50m period (note1) 19.999 20 20.001 ns t22 transmit clock high time 0.3*t21 - - ns t23 transmit clock low time 0.3*t21 - - ns t24 transmit clock to txd[3:0]/txen delay 4 - 11 ns (mii interface) t24 clk50m to txd[3:0]/txen delay 4 - 11 ns (rmii interface repeater only) figure 6-3transmit signal timing relationships at the mii/rmii note 1: the accurate transmit clock frequency shall be 25mhz+/- 50ppm. clk50m should be 50mhz +/- 50ppm. txclk(mii) clk50m(rmii) txd[3:0] txen switch port or pereater port t23 t25 t22 t21
24 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 c.power on reset symbol description min. max. unit t31 pulse width for resetl 1000 - ns figure 6-6 timing constraint resetl resetl t31 d.expansion port symbol description min. max. unit t41 epclk to edat delay time (100m bps) 19 21 ns (epclk and edat outputed from MX98748) t41 epclk to edat delay time(10m bps) 199 201 ns (epclk and edat outputed from MX98748) t42 edat/erxdv sepup time (input to MX98748) 5 - ns t43 edat/erxdv hold time (input to MX98748) 5 - ns figure 6-11 epclk and edat timing relationship epclk edat[3:0] erxdv t41 t43 t42
25 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 symbol description typ. unit t51 multiplexed ledinf period 40 ms t52 latch clock period 8 ms figure 6-12 timing relationship for led display e.led display ledinf[7:0] lnkactsel parsel utl10sel utl100sel t52 t51 link/act link/act partition 10m util 100m ut ......
26 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 figure 6-12 timing relationship for ssram interface(write cycle) f.ssram interface write cycle clk50m cex gwx ma[15:0] md[31:0] t67 t65 t62 t61 t61 t62 t63 t66 t64 symbol description min. max. unit t61 clk50m to cex change 3.5 10.5 ns t62 clk50m to gwx change 3.5 10.5 ns t63 clk50m to ma valid 2.5 12.5 ns t64 clk50m to md low z 3.5 8 ns t65 clk50m to md high z 3.5 8 ns t66 clk50m to md valid 3.5 15 ns t67 clk50m to md invalid 3.5 - ns
27 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 figure 6-12 timing relationship for ssram interface(read cycle) symbol description min. max. unit t71 clk50m cycle time 20 - ns t72 clk50m high pulse width 7 - ns t73 clk50m low pulse width 7 - ns t74 raed to write width 40 - ns t75 clk50m to md low z 0 - ns t76 md setup time 0 - ns t77 md hold time 1.5 - ns t78 clk50m to md high z - 23 ns read cycle clk50m cex gwx ma[15:0] md[31:0] t74 t72 t76 t75 t73 t78 t77 t71
28 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 figure 6-12 timing relationship for eeprom interface g. eeprom interface symbol description min. typ. max. unit t81 esk cycle time - 1280 - ns t82 esk high pulse width - 640 - ns t83 esk low pulse width - 640 - ns t84 esk low to ecs change - - 3 ns t85 ecs low width 2560 - - ns t86 esk low to edi change - - 4 ns t87 edo setup time 5 - - ns t88 edo hold time 1 - - ns esk ecs edi edo t88 t87 t86 t84 t85 t82 t83 t81
29 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 h. clock input clk50m txclk[n] s1txclk s2txclk t94 t91 t92 t93 symbol description min. typ. max. unit t91 clk50m to txclk[n] time interval in mii mode 6 - - ns t92 clk50m period 19.999 20 20.001 ns t93 txclk[n] period in 100m 39.998 40 40.002 ns t93 txclk[n] period in 10m 399.98 400 400.02 ns t94 s1txclk, s2txclk period in 100m 39.998 40 40.002 ns t94 s1txclk, s2txclk period in 10m 399.98 400 400.02 ns
30 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 10.package information sc a l e unit title macronix international co., ltd. d w g . n o .
31 p/n:pm0583 rev. 0.3, aug. 20, 1999 MX98748 revision history revision description page date 0.1 correct mistyping jun/22/1999 modify a/c waveform 0.2 add typical application p2 jun/17/1999 update mii management interface p21 update mii/rmii interface(receive transmit) p22 add clock input waveform p29 0.3 correct mistyping p1,6-16 aug/20/1999 add package information p30 modify eeprom interface t81:1024-->1280;t82:512-->640; p28 t83:512-->640; t85:2048-->2560
m acronix i nternational c o., l td. headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-348-8385 fax:+65-348-8096 taipei office: tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice. 32 MX98748

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